UC San Diego

As the Very-Large-Scale Integration (VLSI) technology advances beyond 7 nm, several challenges arise when designers struggle to fulfill the Power-Performance-Area-Cost (PPAC) requirements of modern complex design and continue the scaling trend in the Post Moore’s Law era. In order to retain the trend of Moore's Law, Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) are introduced together to continue scaling beyond 7 nm using pitch scaling, patterning, and novel 3D cell structures (i.e., Complementary-FET (CFET)). However, standard cell synthesis for novel 3D cell architectures (i.e., CFET and VFET) demand holistic considerations to maximize the area benefit of scaling at the block-level due to the extremely limited routability that comes from the stacked structure and reduced cell height. Furthermore, numerous DTCO and STCO iterations are needed to continue block-level area scaling with considerations of physical layout factors: (i) various standard cell (SDC) architectures (i.e., cell heights, Conventional FET, CFET, etc.), (ii) design rules, (iii) back end of line (BEOL) settings, and (iv) power delivery network (PDN) configurations. The growing turnaround time (TAT) among standard cell design, design rule optimization, and block-level area evaluation becomes one of the major bottlenecks in DTCO and STCO explorations. In this dissertation, We aim to develop novel Computer-Aided Design (CAD) methodologies to resolve the design-technology crisis as scaling beyond 7nm. We propose an SMT (Satisfiability Modulo theories)-based framework to automate CFET SDC synthesis through a novel Multi-row Dynamic Complimentary Pin Allocation Scheme for standard cell height reduction from 4.5T to the extreme 2.5T for DTCO and STCO explorations on emerging 3D cell architectures. Moreover, we propose pin access and routing resource related objectives/constraints for routability to maximize the block-level area benefits. We demonstrate our CFET SDC synthesis framework with extensive studies on various cell architectures (i.e., cell height, multi-row cells, 3D stacking options, etc.), ground design rules (i.e., tip-to-tip spacing, via rule, and minimum area rule), and BEOL configurations for DTCO and STCO explorations. Moreover, we develop a machine learning modeling approach to improve the performance of holistic DTCO and STCO explorations for block-level metrics (i.e., block-level area), which greatly reduce the TAT among standard cell design, design rule optimization, and block-level area evaluation. We organized this dissertation as follows. Firstly, we introduce the novel dynamic complementary pin allocation scheme, and pin accessibility constraints/objectives for routability-driven CFET standard cell synthesis. In addition, we present the improvement of proposed pin accessibility constraints/objectives in the block-level. Next, we present extensive studies on various cell heights, multi-row cell structures, 3D stacking options, ground design rules, and number of BEOLs in the DTCO and STCO explorations. Finally, we introduce the developed machine learning modeling approach to predict DTCO and STCO sensitivity.