UC San Diego

Delta-Sigma modulator ADCs are used extensively in applications where the analog signal bandwidth is narrow compared to practical ADC sample-rates because these ADCs are very efficient and the oversampling relaxes the analog filtering requirements prior to digitization. Conventional continuous-time delta-sigma modulator ADCs require high accuracy building block including low-leakage analog integrators, high-linearity feedback DACs, high-accuracy reference voltages, high-speed comparators, and low jitter clocks. Unfortunately, as process technologies scale and supply voltages are reduced it becomes increasingly difficult to build these circuits. Fortunately however, highly scaled CMOS processes offer very fast, very dense and very low-power digital logic gates. This dissertation presents continuous-time delta-sigma modulator ADCs that consist mostly of digital logic gates. The ADCs are a voltage-controlled ring oscillator based design with new digital background calibration and self-cancelling dither techniques applied to enhance performance. Unlike conventional delta-sigma modulators, they do not contain analog integrators, feedback DACs, comparators, or reference voltages, and do not require a low-jitter clock. Therefore, they use less area than comparable conventional delta-sigma modulators, and the architecture is well- suited to IC processes optimized for fast digital circuitry. Prototype ICs were fabricated in both the 65nm LP and 65nm G+ CMOS processes. The performance of the prototype ICs is comparable to the state-of-the-art in terms of power figure-of-merit but this new architecture uses significantly less circuit area