UC San Diego
High-performance low-power VLSI design
- Author(s): Zhu, Haikun
- et al.
It is widely accepted that, as semiconductor technology continues to evolve, interconnects have dominated over transistors in terms of both performance and power consumption in VLSI. Common belief is that interconnects at the on-chip global level or above in a large extent limit the system performance. While we certainly agree with that, we also believe that local interconnects manifest themselves as critical as the devices in datapath design, if not more so. We intend to show that the interconnect dominance is ubiquitous, and deserves a vertical treatment rather than focusing on a certain level only. In this dissertation, we address several open issues and problems faced by today's designers to reflect the above philosophy: 1) We propose a passive compensation scheme for improving the signal quality over long metal interconnects. The proposed method tries to mimic the behavior of distortionless transmission line by evenly adding shunt resistors between the signal line and ground. Design parameters such as shunt value, spacing and termination are leveraged to achieve the best eye-diagram jitter, and the tradeoff between jitter and eye-opening is also studied. The evaluation of the worst-case jitter and eye-opening is enabled by a fast analytical prediction based on any given bitonic step response, which is new to the best knowledge of the author. 2) We revisit the design of cyclic shifter by introducing two orthogonal new techniques: fanout splitting and cell order optimization using Integer Linear Programming. Both methods emphasize on reducing the interconnect burden in the shifter network, and significant savings on delay and power are reported. (3) We solve the open problem of constructing zero- deficiency prefix adder of minimum depth. This work complements previous studies of the asymptotic behavior of depth-size tradeoff in prefix adders. To designers, it answers the question of how far should we push the timing so as not to incur exponential cost of area and power in prefix adders. Together these contributions made efforts toward high-performance lower-power VLSI design in the nanometer era