UCLA

Advanced packaging is being driven by the need for computing power, thus, the reliability of these systems needs to be addressed. The wide range of organic and inorganic materials used in these systems results in large coefficient of thermal expansion (CTE) mismatch and ultimately high thermomechanical stresses. Moreover, failure due to moisture ingress in harsh environments and challenges of developing novel encapsulations with high step coverage, high throughput and robust barrier properties is another issue that is receiving a lot of emphasis. To improve the performance of the integration platforms, we have developed silicon interconnect fabric (Si-IF) and have shown the advantages of Si-IF compared to conventional platforms in terms of performance, power consumption and heat dissipation. In case of the reliability, Si-IF has many advantages due to the elimination of solder from the platform and the limited number of materials used. All these improvements result in low thermomechanical stresses and elimination of intermetallic compound formation during operation and fabrication in Si-IF. However, the inability to use conventional passivation in Si-IF, leads to a need for a novel passivation to protect any exposed copper that resulted from misalignment from degradation due moisture ingress. In this work, the use of atomic layer deposition (ALD) to deposit Al2O3 thin films for passivation of bonded Si-IF samples was investigated and the effectiveness of this passivation has been verified through experimental testing of fully assembled Si-IF samples for 564 hours under 85%RH and 85 �C testing condition. The change in the electrical resistance of the daisy chains in the samples was less than 3%, showing that this thin film passivation is effective in protecting copper from oxidation. Moreover, we are developing a sophisticated wafer scale system where Si-IF is at the heart of the platform and is connected to state-of-the-art thermal management unit and power platform, moreover flexible connectors are used to make the connection between Si-IF and the outside world. We investigated use of elastomer buffer layer as stress relaxer to improve the reliability of large wafer scale systems under thermomechanical stress. Finite element analysis (FEA) was used to model the wafer scale assembly where Si-IF is bonded to segmented printed circuit board (PCB) and embedded in Polydimethylsiloxane (PDMS) during temperature cycling between +125 �C/-40 �C. Plastic strain within the solder joints were extracted and lifetime prediction of the assembly was performed using Engelmaier model [1]. These analyses show that addition of the PDMS helps reducing thermomechanical stress and strain levels in solder joints and increase the number of cycles to failure of the assembly. Moreover, FEA simulation was used to investigate the effectiveness of PDMS buffer layer in damping the input random vibration. The analysis shows that addition of PDMS to the system effectively damps the input random acceleration and consequently, reduces the stresses that the solder joints experience and improves the lifetime of the system. Damping of the input vibration is due to the low natural frequency of the system when PDMS is utilized as the substrate, moreover; PDMS as an elastomer has a higher damping characteristic due to its hyper elasticity properties as compared to PCB.