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Mitigation of Variability and Reliability Margins in IC Implementation /

  • Author(s): Chan, Tuck Boon
  • et al.
Abstract

Digital VLSI IC design and manufacturing margins continue to increase in light of process variability, circuit reliability and wide operating conditions. In spite of the enhancements from the manufacturing and design sides, there are still substantial margins in terms of manufacturing yield, circuit area and power, and design turn-around-time due to the conservatisms in the design and manufacturing flows. These margins are extremely costly when the benefits from developing the next technology node are only approximately 20% in circuit performance, power and density. To reduce the margins, accurate modeling and assessment of the impacts of variability and reliability are essential. Meanwhile, innovative manufacturing and design techniques must be developed based on comprehensive understanding of the benefits and costs of such new measures. This thesis presents techniques to mitigate variability and reliability margins which can be grouped into three main thrusts : (1) design for manufacturability and reliability, (2) signoff condition optimization, and (3) design-aware manufacturing optimization. In the design for manufacturability and variability thrust, this thesis presents two performance sensor designs for adaptive voltage scaling, which can be used to mitigate the impact of process variations. To reduce the reliability margins for time-dependent dielectric breakdown, this thesis presents a layout optimization technique and a design- dependent reliability analysis framework. In the signoff condition optimization thrust, this thesis presents analyses on the design overheads due to suboptimal signoff conditions in (i) circuit operating voltage and performance, (ii) circuit aging timing model, and (iii) wire parasitic resistance and capacitance models. Meanwhile, the tradeoffs between design quality and signoff margins, and methods to optimize signoff conditions are also included. In the design-aware manufacturing optimization thrust, this thesis presents three distinct techniques to improve manufacturing yield by considering the impact of manufacturing variations on design's timing and leakage power. First, the electrical process window provides a more accurate method to quantify the impact of lithography variability on circuit performance and leakage. Second, design-dependent monitoring provides a cost-effective way to estimate circuit parametric yield based on test-structures available in the early stages of a manufacturing flow. Finally, analysis on the impact of overlay error in double patterning lithography provides guidelines to reduce circuit performance variation

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