UCLA

Compute in memory (CiM) accelerators perform matrix vector multiplications (MVMs) directly inside memory arrays, reducing data movement and improving both energy efficiency and throughput for AI workloads. To reduce the number of conversions, recent designs use multi-bit compute cells. Nevertheless, practical multi-bit CiM still faces a tension between accuracy, efficiency, and re-writeability, since multi-level NVM based designs suffer from nonlinearity and poor re-writeability, while multi-level activation based DRAM / SRAM macros are limited by mismatch and low accuracy. This work introduces a per-cell DAC based CiM macro that combines the density of multi-level NVM with fully re-writable DRAM weights to break the trade-off. Each bit cell embeds a compact 6-bit CTT based current mode DAC, calibrated in-situ through a write verify write loop, together with a 1T(1C) embedded DRAM. Post-layout simulations of a 576×256 macro in 22nm FDSOI project 49.9 8b-TOPS/W, and 8.96 8b-TOPS/mm2, while system level evaluation on CIFAR-10 and CIFAR-100 with ResNet-50 shows less than 0.2% accuracy loss relative to a digital baseline, without the need for any Hardware-aware Training.