UC San Diego

Traditionally, datacenter networks are constructed with electronic packet switches, which forward data in a distributed manner. However, packet switches are running in to serious scaling challenges due to the massive growth in bandwidth requirements within major datacenters. One possible solution to this situation is to use optical circuit switching, which has significant potential for both power and cost savings.

However, circuit switching is a completely different paradigm from packet switching, and as such effectively utilizing circuit switching requires work at all layers in the network, including the network architecture, switches, transceivers, network interfaces, and protocols.

This dissertation validates the thesis that developing a NIC capable of precision admission control and characterizing its performance can lead to practical sub-microsecond circuit-switched networks at scale. Specifically, this dissertation presents novel contributions to two key system-level issues inherent in utilizing optical circuit switching in datacenter networking applications.

The first contribution of this dissertation quantifies the system-level reconfiguration time of an optically circuit-switched link. This work is critical for understanding how to build optical links using high speed optical switches and how to integrate these links into a datacenter environment. This includes a discussion of system-level reconfiguration time and link-level measurements of an optically switched link, including bit error rate (BER) characterization of a 25 Gbps link utilizing a burst-mode receiver, switched by a nanosecond-scale silicon photonic switch.

The second contribution of this dissertation is the development of a network interface controller (NIC) that can precisely control the injection of packets into an optically-switched network. This work describes and quantifies the performance of a novel high-performance, open-source, FPGA-based NIC called Corundum. This NIC is designed to precisely control the injection of packets from multiple queues into a circuit-switched network using a hardware-based scheduler. The platform provides the flexibility to implement high precision time synchronization as well as perform link-level characterization including BER measurements. The development of such a network interface can lead to practical sub-microsecond circuit-switched networks at scale.