UCLA

Over the last decades, conventional scaling (Moore’s law) has provided continuous improvement in semiconductor device/circuit technology. FinFETs, featuring superior electrostatic control compared to planer FETs, have been the mainstream technology for the

front-end-of-line (FEoL) application since the 22-nm node. Process-induced performance variation, which is already a key limit in 7/10-nm node FinFETs, is becoming even more severe in beyond 5-nm node. Furthermore, FinFETs’ analog/RF performances are inferior to those in bulk and SOI transistors, preventing their applications in the system on chip (SoC) designs. In this work, 3D source/drain extension (SDE) doping profile control technique, developed for ION/IOFF enhancement in 7/10-nm node FinFET, is proposed as an effective method for variability suppression and digital/analog performance enhancement in the 3-nm node. The methodology of 3D doping profile optimization and governing physics are systematically analyzed.

In addition to transistor scaling, wafer-level packaging (WLP) has also been widely accepted as a pathway to further increase the device density. Active device integration in the back-end-of-line (BEoL) has been proposed to enhance the interconnect bandwidth, design flexibility, and reduce power consumption. Multi-layered molybdenum disulfide (MoS2), featuring a finite bandgap, high mobility, and possible CMOS BEoL compatible (<400 �C) synthesis process, is a promising candidate for such an application. One of the major roadblocks in MoS2 FET’s fabrication is the lack of the controllable doping process for S/D formation. This work demonstrates a carrier control technique in MoS2 by introducing substitutional Nb. The impact of high concentration Nb is quantified to precisely modulate the carrier density. Electrical characterizations show that a high carrier density (>2�1020 cm-3) can be achieved, favorable for S/D formation with low access resistance. The relations between high concentration Nb and mobility, contact resistivity, and bandgap are also analyzed to guide MoS2 transistor design.