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Distributed Circuits for Ultra-Wideband Communications Systems

  • Author(s): Fang, Kelvin Caiwen
  • Advisor(s): Buckwalter, James F
  • Asbeck, Peter M
  • et al.
Abstract

Emergent millimeter-wave (mm-wave) integrated technologies will find applications where the ample available bandwidth offers a significant performance advantage. Ultra-wideband (UWB) signals that cover multiple octaves improve resolution in imaging systems, high-frequency instrumentation, and radar. Additionally, high data rate communications systems will emphasize amplification across several frequency bands in a single amplifier. Conventional tuned amplifiers have difficulties satisfying such large bandwidth requirements due to their inherent gain-bandwidth tradeoff. On the other hand, distributed amplifiers (DAs) provide an effective solution with their large fractional bandwidths (FBW) and low gain variation and sensitivity to mismatch.

In this dissertation, several distributed circuit design techniques are presented to improve the performance of wideband transceiver front-end system blocks. First, a novel supply-scaling technique is proposed to improve the efficiency of distributed power amplifiers. A single-ended, eight-stage DA is designed in a 90-nm SiGe BiCMOS process, and the fabricated amplifier exhibits measured 12 dB gain over 3 dB bandwidth from 14-105 GHz. The peak saturated output power (Psat) is 17 dBm with peak power-added efficiency (PAE) of 12.6% at 50 GHz and 3 dB power bandwidth greater than 70 GHz. This is the largest single-ended output power, efficiency, and power bandwidth reported in the literature for a SiGe BiCMOS DA.

Based on the supply-scaling technique, a tunable distributed active quasi-circulator (QC) with integrated power amplifier (PA) is proposed. The fabricated QC in a 45-nm CMOS SOI process provides more than 40 dB suppression between transmit (TX) output signal at the antenna (ANT) and TX leakage into the receive (RX) port over a tuning range of 5.3-7.3 GHz in small-signal operation. The TX output achieves peak power of 18 dBm and 12% PAE at 6.3 GHz, and large-signal TX-RX suppression is optimized across power level. Compared to the literature, the distributed active QC has the largest output power and fractional operating bandwidth among circulators with >30 dB isolation.

Finally, a hybrid CMOS supply-scaled distributed amplifier (SSDA) taking advantage of higher operating voltage and distortion cancellation of scaled PMOS devices and an integrated distributed transceiver front-end (DTFE) are presented. The hybrid SSDA is designed in a 45-nm RF CMOS SOI process and achieves peak Psat of 17.5 dBm and PAE of 20.2% with low third-order intermodulation (IM3) and amplitude-phase (AM-PM) nonlinearities over a 3 dB bandwidth of 10-82 GHz. The DTFE utilizes time-domain duplexing (TDD) to drive a shared antenna port for TX and RX modes. It achieves TX gain of 11.7 dB from 12-76 GHz with peak output power of 17 dBm and PAE of 14.2% and RX gain of 9 dB from 11-77 GHz with minimum noise figure (NF) of 6.2 dB. 5 GHz wideband 16-QAM modulation is demonstrated in the RF CMOS SOI circuits for data rates exceeding 20 Gb/s. The hybrid SSDA leads all reported silicon DAs in peak power efficiency and output third-order intercept point (OIP3), and the transceiver front-end circuits achieve over 3x greater data rates than other published wideband silicon PAs.

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