UCLA

The cost per die benefit of semiconductor technology scaling that has driven Moore's law is being threatened by increasing manufacturing cost. Masks, which reproduce circuit patterns on the wafer, are the biggest contributor to this manufacturing cost. The need to print sub-wavelength patterns on the wafer and ensure tight dimension control has significantly increased the cost and complexity of mask manufacturing that consists of three key steps: mask data preparation, mask write and mask inspection. In this thesis, we propose novel computational approaches to reduce mask manufacturing cost by using design information to reduce the pessimism of mask manufacturing processes. We further explore benchmarking of computational mask data preparation algorithms.

To reduce the pessimism of geometric approaches to estimate lithographic process window, we propose electrical process window (EPW), which accounts for electrical specifications of the circuit layout such as delay, power and static noise margin, thereby reducing pessimism by 1.5 to 8×. To reduce the pessimism in mask inspection, which can take up as much as 30% of the total mask manufacturing time, we propose design-aware mask inspection. We first locate non-functional features in a circuit layout, and then use that information along with the timing information of the design, to assign criticality to different layout shapes. This information can be exploited by mask inspection tools to reduce defect review time and first pass yield of masks. Our results demonstrate 39% reduction in the number of defects reported by the inspection tool and 19%-point improvement in first pass yield of a critical polysilicon mask.

Mask fracturing is a key component of mask data preparation that determines the e-beam shots required to write the mask. Since shot count is directly proportional to mask write time, reducing shot count is a key

objective for mask fracturing solutions. To evaluate the suboptimality of modern model-based mask fracturing heuristics, we propose an integer programming based benchmarking method and an optimal benchmark generation method. Our methods show that even a state-of-the-art prototype [version of] capability within a commercial tool for e-beam mask shot decomposition can be suboptimal by as much as 2.3X for real mask shapes and by 6X for generated benchmarks.

Extreme ultraviolet (EUV) lithography, a front-runner to replace the incumbent 193nm lithography, suffers from hard-to-repair mask blank defects. To mitigate these defects, we propose a defect avoidance method based on random walk and gradient descent that can allow mask makers to use masks with even 30 defects without any significant yield impact for a 14nm polysilicon layer of a design. However, at sub-10nm technology node, tight CD tolerances and dense layouts would make the task of using a defective mask blank challenging. To aid the design of EUV layouts that are robust to mask defects, we propose a new metric called critical density, which can quickly evaluate the robustness of EUV layouts. Using this metric, we show that regularity actually reduces the ability of EUV layouts to tolerate mask defects.