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Design studies of nanometer-gate low-noise amplifier near the limits of CMOS scaling

Abstract

As many millimeter-wave (mm-wave) applications has been proposed for the next generation communication systems recently, CMOS has become a technology of choice due to its increasing RF performance by transistor scaling and many inherit merits including low cost, low power and high level of integration. This dissertation presents a comprehensive design study of power-efficient CMOS low- noise amplifiers (LNAs) near the scaling limits. Starting with an introduction to the mm-wave system applications and enabling technologies, the current status of research and development on technology candidates for mm-wave applications has been surveyed with the focus on the Si CMOS. The effect of CMOS scaling has been studied using state-of-the-art 40- and 20- nm MOSFETs, and 20-nm double- gate (DG) MOSFET (a generic form of FinFET), and a 10-nm DG MOSFET at the scaling limit. A two-dimensional device simulator TCAD is used to extract various RF performance parameters at 60 GHz. To take both the amplifier gain and noise figure into account, a new design methodology using noise measure as a figure of merit is developed. Excellent noise performance has been achieved with the identified optimal biasing for power-efficient low-noise amplifications at 60 GHz. The effect of the gate resistance to the overall noise performance has been investigated, which has been found to be insignificant as long as the device width per gate finger is constrained. The performance trends of CMOS LNAs near the scaling limit has been studied with correlations made to the published hardware data. It is further shown that the RF performance of CMOS LNAs can be greatly enhanced by down scaling to 10 nm, using the more scalable structure of DG MOSFETs, with sub-1-dB noise figures at 60 GHz and beyond

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