UC San Diego

Continuous scaling of feature sizes in CMOS integrated circuits (IC) pushes the design performance envelope as well as design complexity higher with each successive technology node. Advancements in materials and optics of the manufacturing process enable the scaling and manufacturability of devices in ICs. As device feature dimensions approach the physical limits of lithography and the manufacturing process, the smallest geometric and material variations manifest as design-level performance and power variability. One of the main pathological effects of IC scaling is the increase in design variability as a fraction of performance with each technology node. This design variability directly affects IC parametric (i.e., performance-limited) and catastrophic (i.e., defect-limited) yield, and consequently, IC cost. To address the increase in manufacturing variability in deep-submicron (DSM) technologies and to improve IC yield, a new design for manufacturability (DFM) paradigm has emerged in the recent past. The DFM paradigm encompasses a set of design methodologies that address manufacturing and process non-idealities at the design level to make ICs more robust to variations. DFM is also interpreted as a set of post-layout design fixing techniques that enhance and ease manufacturability. In general, the objective of DFM is to improve IC yield and cost by increasing manufacturing-awareness in the design phase, as well as design-awareness in the manufacturing phase. To achieve this dual objective of DFM, design must be driven by models of variation in the manufacturing process and the manufacturing process, must be made aware of the design intent. Variations in the IC manufacturing process are manifested as (1) deviation from the intended shapes of IC geometries, and (2) variations in impurity (i.e., dopant) concentrations. These variations are composed of systematic and random components. The systematic component of variation can be attributed to specific sources in the manufacturing process, while the random component is usually a result of confounding of several sources of variation and cannot be attributed to specific sources. A significant fraction of the total variation in shapes of IC geometries is systematic in sources such as focus, exposure dose, lens aberrations, etc. The objective of this thesis is to model the impact of the raw sources of variation at the mask making and wafer pattern transfer phases in manufacturing. The primary goal in the associated research is to develop models that can drive systematic variation-aware design. We propose techniques to model the impact of mask-level and wafer-level sources of variation on IC geometries. At the mask-level, proximity effects and resist heating caused by electron- beam writing are the two main sources of mask critical dimension (CD) errors. We propose a novel methodology to model resist heating caused by electron-beam writing on the mask resist. We use the resist heating model to drive temperature-aware mask writing schedules that minimize resist temperature, and consequently minimize mask CD error. Sub-wavelength optical lithography in sub-100nm technology nodes is enabled by resolution enhancement techniques (RETs) that allow patterning of layout features on silicon wafers. Optical proximity correction (OPC) is the most prominent RET used to compensate a design layout for optical and process effects prior to mask making and lithography. OPC modifies the shapes of layout features, and consequently increases mask complexity and cost. We develop a model of post-OPC mask cost of design features, to drive design-aware mask cost optimization. Despite advanced RETs and illumination techniques, several sources of variation in the pattern transfer process result in variations in chip-level performance and power. At 45nm and below, accurate design-level performance and power analyses must consider litho-simulated non-idealities in patterning. However, the simulation of exposure, resist and etch processing steps in lithography is computationally expensive to perform at chip-scale, and essentially infeasible during iterative design optimization. In this thesis, We develop a predictive model of post-OPC linewidth of devices in standard cells across the process window. The predictive model is fast, accurate and highly scalable, enabling its use in the design phase at full-chip scale without actually performing OPC and litho simulation. Last, we demonstrate the use of predictive linewidth models in fast and accurate leakage estimation and optimization. First, We discuss the use of through-focus systematic linewidth models to achieve accurate leakage estimation. We then discuss a novel detailed placement perturbation approach that leverages systematic pitch and focus interactions to improve leakage in light of systematic linewidth variation. These two methods demonstrate the use of predictive models of variation in driving variation-aware design analysis and optimization