UC San Diego

Two obstacles facing the widespread commercial implementation of III-V semiconductors for use as the channel in MOSFETs are the large density of interface trap states at the III-V/oxide interface and challenges associated with deposition of high-k materials for use as the gate oxide on III-V surfaces. Interface trap states are physical defects at the semiconductor-oxide interface that result in electronic band gap states. These defects states typically arise from metallic bonds, bond angle strain, undercoordinated atoms, or contamination on the semiconductor surface. Additionally modern MOSFETs use tri -gate, or finFET, architectures which usually utilize orthogonal crystallographic planes, such as the (001) and (110) faces, simultaneously. It is crucial to develop methods to clean and passivate both of these crystal faces to allow for high nucleation, aggressive EOT scaling, and low Dit of the high-k oxide. In this work passivation methods for both InGaAs and GaAs (001) and (110) surfaces were developed. STM was utilized to characterize the atomic bonding configuration of the passivants on both the (001) and (110) surfaces, STS was used to characterize the density of states of the passivants, and XPS was used to determine the elemental composition and oxidation states of the surface atoms. It was determined that both surfaces contain inherent defects which can be passivated initially with a reductant, TMA. But chemisorption of TMA on these surfaces creates, directly or indirectly, CB band edge states which can be passivated by a small dose of oxidant. Ex situ and in situ native oxide removal and surface cleaning techniques were examined on the (001) and (110) surfaces. The ex situ wet BOE preferentially etched the (001) compared to the (110) surface. An in situ surface clean, developed by Carter et al. and Chobpattana et al. for the (001) surface, was found to also be effective on the (110) surface which is ideal when depositing HfO₂ on 3D InGaAs structures. H plasma induced etch damage resulted in a large Dit but by including TMA in the surface clean this etch damage was prevented. CV meaurments were made to correlate observations made with STM and STS to electrical device data