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Dynamic Instruction Fusion


Energy efficiency in modern microprocessor design is a first order concern. Every facet of the microprocessor needs to be optimized now to be efficient in accesses, storage, and instruction execution. Dynamic Instruction Fusion provides a means to accomplish all three of these goals. By leveraging register re-use within typical instruction streams, whether generated through the use of a trace cache, or through wide issue instruction logic, it is possible to simultaneously reduce both the number of accesses to the register file, as well the number of instructions stored within the instruction window.

On average, Dynamic Instruction Fusion can reduce the number of instructions scheduled by ~ 48%, while simultaneously reducing the number of accesses to the register file by ~30%. This reduction in both the number of register file accesses and instruction window entries directly corresponds to a saving in energy in the register file.

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