UCLA

With an ever-widening signal spectrum and incorporation of multiple standards that share the available spectrum at the same time, research towards building wideband analog-to-digital converters (ADCs) has gained significant momentum. Furthermore, with an aim to improve spectral efficiency, increasingly complex modulation schemes are being invoked having high peak-to-average ratios, the latter translating to high dynamic ranges for the received signals. Consequently, the ADCs deployed in these receivers need to be of quite high precision as well. With these two primary goals for ADCs (high bandwidth, high resolution) in mind, this thesis presents a few different techniques for achieving them.

In the first part of this thesis, we shall explore the art of dithering to linearize an A/D converter system. In particular, a digital-signal conditioning technique (using subtractive dither) is developed as a stepping-stone for a high resolution system. The effects of filtering the dither signal to shape its spectral content outside the signal band while maintaining its benefits are studied in detail. Design strategies for finite impulse response (FIR) filters that accomplish spectral shaping as well as allay quantizer non-linearity are derived theoretically.

In the second part of this thesis, the proposed dithering technique is used for linearizing an ADC system that is intrinsically non-linear, namely a VCO-based ADC. Ring voltage-controlled oscillator (VCO)-based ADCs have surfaced as elegant alternatives to the traditional $\Delta-\Sigma$ modulators primarily due to their mostly digital nature. They offer low power, low area and simplicity of design benefits. However, they are known to be notoriously non-linear that can be attributed to the non-linear nature of the frequency-voltage tuning curve of the VCO. In the proposed scheme, the ring VCO-based ADC is preceded by a coarse flash ADC. The former processes the quantization error (residue), a signal with much smaller dynamic range, from the coarse ADC thereby lessening the impact of the non-linearity. The proposed dithering technique further helps in alleviating the non-linearity. It helps condition the signal to the VCO input to appear as white noise thereby eliminating spurious signal content arising out of the VCO nonlinearity. The technique, thus obviates the need for power-hungry digital calibration techniques or expensive front-end loop-filters. A prototype implementation (in 65nm CMOS) based on the technique achieves 10-b ENOB in digitizing signals with 50MHz bandwidth consuming 8.2mW at an FoM of 90fJ/conv.step.

In the third part of this thesis, a very popular technique of bandwidth enhancement through time-interleaving multiple A/D converters is examined. Time-interleaved A/D converters enable high conversion bandwidths with quite high precisions. However, inevitable mismatch errors typical of any integrated circuit fabrication process degrades the achievable dynamic range of such A/D converters. Multiple techniques have been proposed over the past two decades to alleviate the problems of mismatch errors. This chapter takes a detailed look at most of these techniques bringing out their strengths and weaknesses. The chapter provides a hitherto unavailable common platform to look at analog and digital intensive techniques towards solving this issue motivating the development of a novel solution to this problem in the subsequent section.

In the fourth chapter, a power-efficient technique to combat mismatches for time-interleaved systems is proposed. The proposed technique adaptively selects finite impulse response filters that take advantage of the signal characteristics. The sub-band outputs from the ADC are passed through these filters to correct for errors at a minimal hardware expense. Simulation results substantiating the claims and thorough analyses of the technique are subsequently presented to highlight the efficacy of the technique.

Chapter 1 of this thesis has been published in full in the International Conference on Acoustics, Speech and Signal Processing(ICASSP)}, 2013. The dissertation author is the primary investigator and author of this paper. Professor Sudhakar Pamarti supervised the research which forms the basis for this paper.

Chapter 2 of this thesis is a reprint of a paper under preparation to be submitted in part or in full to the IEEE Journal of Solid-States Circuits (JSSC) . The dissertation author is the primary investigator and Professor Sudhakar Pamarti supervised the research which forms the basis for this paper. By the virtue of being (or to be) independent papers, there is a slight degree of overlap in content between Chapters 1 and 2, but this is essential to maintain the continuity of the chapters.

Chapter 3 of this thesis is a reprint of a paper under preparation to be submitted in part or in full to the IEEE Transactions of Circuits and Systems-1 (TCAS-1). The dissertation author is the primary investigator and Professor Sudhakar Pamarti supervised the research which forms the basis for this paper.

Chapter 4 of this thesis is also a reprint of a paper under preparation to be submitted in part or in full to the IEEE Transactions of Circuits and Systems-1 (TCAS-1). The dissertation author is the primary investigator and Professor Sudhakar Pamarti supervised the research which forms the basis for this paper.