UCLA

Gate-level characterization (GLC) is the process of characterizing each gate of an integrated circuit (IC) in terms of its properties, such as power and delay. It is a key step in the IC applications regarding cryptography, security, and digital rights management. However, GLC is challenging due to unpredictable process variations, gate correlations, and difficulties to scale to large designs.

We have developed a new approach for hardware and system security using consistency-based GLC and statistical analysis. In particular, we first conduct input vector control, test point insertion, and thermal conditioning to impose extra variations to the IC properties and break the correlations among gates. Then, we partition the circuit into small segments and characterize the gate-level IC properties in each segment. Finally, we employ statistical methods to analyze the consistency of the gate-level properties, both intra- and inter-segments, to identify and diagnose malicious modifications (e.g., hardware Trojans) or other misconduct (e.g., IC counterfeiting) made by an adversary.

Based on our research findings in the consistency-based GLC, we develop a group of hardware security applications, including (1) hardware Trojan detection and diagnosis; (2) hardware metering and digital rights management; and (3) remote and in-field wireless security. The effectiveness of the consistency-based GLC in varieties of applications indicates that it is the foundation and enabler for reliable hardware and system security techniques.