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Off-chip wire distribution and signal analysis


With the steady progress of high performance electronic systems, the complexity of the electronic systems grows continuously and new features like high-speed, low power and low cost, become the key issues. The interconnection in the electronic systems distributes the power, clock and transfers the electrical signals among numerous components. As the feature size of microelectronic technology becomes smaller, the design and analysis of the interconnection are more important for the performance and cost of the system. The escape routing design is a new important problem in the interconnection design because the number of chip/package input/output (I/O) pins has continuously been growing for high-speed high-performance system. The traditional escape routing strategy and several improvements, pins/pads special placement and routing resource exploration, could not handle large number of I/Os efficiently and usually require increased cost. We introduce a novel concept, escape sequence, develop efficient escape routing strategies based on the new concept and model the escaping wires using 3D extraction. For square grid array, we formulate and solve a maximum flow problem to analyze the escape bottleneck in area array. The layer count can be decreased dramatically by optimizing the I/O escape sequence. Two new escape routing strategies, central triangular escape routing and two-sided escape routing, are proposed and the number of escape routing layers could be reduced dramatically. We implement an automatic escape routing program to verify our analysis and to compare different escape sequence strategies. The escaping wires could be modeled as frequency dependent RLGC circuit for signal performance analysis. For hexagonal area array, we analyze its preponderant properties that the hexagonal array could increase the density of I/Os in the array remarkably. We propose three escape routing strategies for the hexagonal array: column-by-column horizontal escape routing, two- sided horizontal/vertical escape routing, and multi- direction hybrid channel escape routing. We can escape I/ Os in the hexagonal array in the same or less number of routing layers compared with square grid array. Therefore, we could reduce the number of escape routing layers as well as increase the density of I/Os. The eye diagram prediction is an important problem in the interconnection analysis because an eye diagram provides the most fundamental and intuitive view to evaluate the signal quality of high-speed communication. The traditional method to obtain the eye diagram involves performing a time domain simulation. It requires a very long simulation time and usually could not accurately characterize the communication systems because the limited length pseudorandom bit sequence (PRBS) as the input stimulus. Several eye diagram prediction methods, analytical techniques, analysis based on unit pulse response and analysis based on step response, have their application constraints because of their assumptions and usually could not handle general systems. We introduce an efficient and accurate method, the accumulative prediction method, to predict the eye diagram for high-speed signaling systems. We use the step response of the signaling system to extract the worst-case eye diagram, including the eye opening and timing jitter. Furthermore, this method generates the input data patterns which produce the worst- case inter-symbol interference. The main advantage is that this general-purpose method can handle signals with asymmetric as well as symmetric rise/fall time. Furthermore, the complexity of the proposed method is linear O(n), where n is the number of time points of step response. This method can be applied to analyze the signal performance in escape routing. It is very useful to analyze various high speed signaling systems

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