UC San Diego

In advanced technology nodes, aggressive device scaling along with fundamental physical (lithographic patterning, CMP, reliability, variability, etc.) and circuit (crosstalk, delay, etc.) limitations remain. As a result, ever-more complex design rules introduce challenges for the design automation tool flow, especially placement and routing (P&R). Moreover, as feature sizes shrink, there is increased difficulty of modeling the behavior of devices, as the proximity of devices significantly affects device performance.

The increasing complexity and difficulty lead to three challenges. First, turnaround times of both automated design tool flow and manufacturing increase due to (i) model-hardware miscorrelation and (ii) miscorrelation in different P&R tool stages. Second, direct application of academic works is limited because research works focus more on abstracted and simplified problems, while leaving the key elements of such abstraction and simplification as open questions. Third, the gap between academia and industry is widening because academic works tackle highly-dependent problems with independent and disjoint efforts. For example, the open literature is dominated by isolated research works on global routing and detailed routing, where the crucial correlation between these stages is ignored.

To address these three challenges, this thesis presents research works in three directions: (i) detailed placement optimization for correlation improvement; (ii) key elements of enablement for routing in advanced technology nodes; and (iii) an open source, end-to-end global-detailed routing tool that gives a first-ever academic routing flow for advanced technology nodes.

To improve correlation with detailed placement optimization, this thesis presents two works: (i) an optimal multi-row detailed placement optimization for neighbor diffusion effect mitigation; and (ii) an in-route, pin-access driven detailed placement refinement for detailed routing convergence improvement.

To enable academic research on routing, this thesis presents two works on key elements: (i) a geometry-based design rule check engine and (ii) a dynamic programming based pin access analysis engine.

To narrow the gap between academia and industry in routing, this thesis presents an end-to-end, complete routing flow for advanced technology nodes. Implementation of the routing flow along with the aforementioned design rule check engine and pin access analysis engine are open-sourced under a permissive license.