UCLA

Modern digital communication systems target satisfying multiple standards and different operating scenarios. Applications include read channels of data storage systems, PCIe links, FPGA I/Os, and multi-standard radios. This stimulates the research on reconfigurable analog-to-digital converters (ADCs) to serve as a key building block at the front-end of such systems. Conventional reconfigurable designs suffer from poor figure-of-merit (FoM) scaling with different resolutions, which reduces their flexibility. The limited efficiency of these techniques is attributed to the fact that they fix the ADC architecture for all configurations, whereas the optimum architecture depends on the target resolution. This dissertation introduces an architecture reconfigurable ADC that efficiently covers a wide range of resolutions by configuring the ADC to the proper architecture for each resolution. This leads to a reconfigurable ADC nearly as efficient as dedicated designs in both area and power.

Device matching is the heart of precision analog design. Basically, well matched devices come at the expense of larger die, parasitic capacitance and power consumption. Instead of only sizing the devices to achieve the desired accuracy, the intrinsic accuracy of an area efficient converter is designed worse than its resolution. Before or during chip usage, self-calibration automatically detects and corrects for elements mismatches and leads to reduced silicon area and improved yield. This dissertation investigates the efficiency of using body voltage trimming calibration for data converters. The tradeoffs of this technique are studied in details. Suggested methods have been presented to extend the use of bulk voltage trimming beyond technology limitations with minimal area and power overhead and no special technology requirements. The study shows that best results are achieved when mixing bulk trimming with other calibration techniques.

Two prototype chips are implemented in 65-nm CMOS to verify the results of this study. The first chip is a 2.5-10GS/s reconfigurable flash ADC. The ADC can be configured to work as a 3-bit, a 4-bit, or a 5-bit ADC with worst case integral nonlinearity (INL) and differential nonlinearity (DNL) of 0.48LSB and 0.35LSB respectively. The ADC achieves a figure-of-merit of 0.46pJ/conv-step and the active area is 0.13mm². The second chip is a 1.5-4GS/s "architecture" reconfigurable ADC. The ADC covers resolution range from 3b to 7b, and achieves a figure-of-merit of 0.46pJ/conv-step at 7-bit and the active area is 0.15mm².