Skip to main content
eScholarship
Open Access Publications from the University of California

Physical planning to embrace interconnect dominance in power and performance

  • Author(s): Wang, Renshen
  • et al.
Abstract

The growth of computer performance by Moore's law is currently limited by power consumption and waste heat removal. As feature size scales down, dynamic power of integrated circuits (IC) is increasingly dominated by interconnect wires. Reducing this power has become a focusing target for computer architects and circuit designers. In this dissertation, we study on two phases in IC design flow, floorplanning and interconnecting, to address the challenges on interconnect latency and power. The first and most direct way is to shorten the interconnect lengths. Current IC chips are manufactured on a 2-dimensional silicon die. Moving to 3-dimensional enables us to make the same circuit within a much smaller foot print, and therefore greatly reduce interconnect power. For 3-D floorplanning, we study the computational complexity of placing cuboids in 3-dimensional space under adjacency constraints. We use the basic graph-to-floorplan formulation and a 2.5-D variation with more strict layer constraints. In both cases, we find the problem is NP- complete by reductions from known NP-hard problems. The results, combined with previous work on the 2-D counterpart, show the fundamental hardness residing in 3-D structures, and reveal possible challenges in design complexity moving from 2-D to 3-D. Another way, when interconnect distances can no longer be reduced, is to minimize the wires involved in communication actions. Most multi-component system-on-chips use bus or bus matrix to connect all the sub-systems. Complying with standard bus protocols, we devise a bus matrix synthesis scheme to minimize dynamic power on communications, while maintaining the bandwidth capability and routing resources. The geometric basis is the shortest-path Steiner graph extended from Steiner arborescence (shortest -path Steiner tree), where optimized graph structures are used to replace the large wire nets in traditional bus architectures. Experimental results show that near-optimal communication power can be achieved without consuming excessive on-chip resources

Main Content
Current View