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Accurate estimators and optimizers for networks-on-chip

  • Author(s): Samadi, Kambiz
  • et al.

Networks-on-chip (NoCs) are emerging as the de facto on- chip interconnection fabric of choice for both general- purpose chip multiprocessors (CMPs) [68, 108, 110] and application-specific multiprocessor systems-on-chip (MPSoCs) [43, 78]. When the number of on-chip cores increases, the need for scalable and high-bandwidth communication fabric becomes more evident [43, 78]. Another megatrend in advanced technologies is that power has become the most critical design constraint [57, 6]. In this thesis, we present integrated research on NoC power, performance and area modeling to enable efficient early- stage design space exploration that improves our understanding and characterization of the NoC power-area- latency design space. The intellectual merit of our proposed approaches stems from their balanced attack on necessary NoC-specific techniques for (1) architecture- level estimation (to provide correct optimization objectives) and (2) architecture-level optimization (to expand the achievable design envelope). In the architecture-level estimation thrust, we develop new architecture-level estimation methods that are accurate and easily portable to different router microarchitectures. Also, our proposed models can accurately capture implementation effects. Specifically, we develop (1) automatic generation of accurate architecture-level estimation models; (2) portable models across different microarchitectures; and (3) accurate modeling of application-specific integrated circuit (ASIC) implementation flow choices and their impacts. In the architecture-level optimization thrust, we develop (1) trace-driven optimizations of NoC configurations for actual traffic behavior and workloads; and (2) simultaneous floorplan optimization of chip multiprocessors across multiple products. The broader impact of this thesis lies in helping NoC intellectual property (IP) and MPSoC designers reduce design turnaround time in addition to product chip area, delay and power metrics. This will enable the design of more complex and functional products within a given cost and power envelope. With our models, we also develop an infrastructure to extract necessary model inputs from several reliable sources (e.g., Liberty [8], SPICE [15], etc.) to ease the updating of models as new technology files become available. Finally, a significant contribution of this thesis lies in providing a publicly available framework for accurate and efficient NoC modeling [12]

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