UC San Diego

The thesis presents X- to W-band arrays implemented in silicon technologies for different phased-array applications. An 8-20 GHz two-channel dual down-conversion receiver with selectable IF for interference mitigation is presented for digital beamforming applications. The receiver is fabricated using a 0.18[mu]m SiGe BiCMOS process and results in a channel gain (I and Q paths) of 46-47 dB at 11-15 GHz and > 36 dB at 8-20 GHz with an instantaneous bandwidth of 150 MHz. The measured NF is < 4.1 dB (3.1 dB at 15-16 GHz). The measured OP1dB is -10 dBm and the input P1dB is -56 to -40 dBm at 15 GHz depending on the gain, which is sufficient for satellite applications. The on-chip channel-to-channel coupling is < -48 dB. The measured EVM is < 3% for a 1 Msps QPSK modulation at 8-20 GHz, and < 1.8% for a 0.1, 1 and 10 Msps QPSK, 16QAM and 64QAM modulations at 15 GHz. The chip has ESD protection on the RF and DC pads, consumes 70 mA per channel from a 3.0 V power supply and is 2.6x2.2 mm², including all pads. A 15 GHz 8-element phased array with a NF < 3.9 dB is also demonstrated with multiple simultaneous beam performance using digital beamforming. In another project, a silicon-based 8-element phased array based on an All-RF beamforming topology is integrated together with the antennas and digital control circuitry on a single Teflon board. The chip-on-board package, together with 8 X/Ku-band RF inputs and one RF output in a 2.2x2.5 mm² area, and the appropriate grounding and Vcc connections, are modeled using a 3-D EM solver. The design results in a low coupling between the different RF ports, and ensures stability even with a channel gain of 20 dB at 12 GHz. The measured patterns show a near-ideal performance up to a scan angle of 60° with an instantaneous scanning bandwidth of 11.4-12.6 GHz (limited by non true-time delay connections between the antennas and the chip). Temperature tests indicate that the silicon chip maintains excellent phase stability and rms phase error up to 100°C. Finally, the first mm-wave wafer-scale silicon power amplifier array is implemented using 0.13 um BiCMOS technology. The power combining is done in the free -space using the high efficiency on-chip antennas. First, a W-band SiGe power amplifier is designed and fabricated together with a high-efficiency on-chip microstrip antenna. The power amplifier consumes 120 mA from a 1.7 V supply and the antenna/amplifier results in an effective radiated power (EIRP=PtGt) > 10 dBm from 88 to 98 GHz, with a peak of 14.6 dBm at 92 GHz. Then, a 3x3 power amplifier array is demonstrated with an equivalent isotropic radiated power (EIRP) of 33-35 dBm at 90-98 GHz. This results in a total on-chip power of 21-23 dBm, and a total radiated power of 17.5-19.5 dBm. The our knowledge, this is the highest power (and EIRP) achieved from a single silicon chip at millimeter-waves. The measured patterns of the array show single-mode operation and 1̃00% free-space power-combining efficiency with a 3-dB beamwidth of 28° and a directivity of 15.5 dB (gain of 12 dB). The total power-combining efficiency including the antenna losses is 45±10%. It is shown that by using this technique high power (1-2 W) millimeter-wave transmitters with phased array capabilities can be realized in silicon technologies which will be compatible with best III-V solutions. The application areas are in millimeter-wave transmitters and wafer-scale phased arrays