UC Santa Cruz

As process technology continues to shrink, Integrated Circuits (ICs) can hold more memories on the chip to improve overall system performance, efficiency, and cost. Most academic IC design methodologies are inhibited by the availability of memory designs and timing characterizers. Many standard-cell Process Design Kits (PDKs) are available from vendors and foundries, but these PDKs do not come with any memory compilers or characterizers, while more expensive solutions only provide memory models with limited configurations and restrictive licenses. This thesis showcases OpenRAM, a characterization methodology and the author’s contributions. The author added the characterization methodology to OpenRAM to be able to generate timing and power characterizations through SPICE simulations. He also reorganized the memory modules and rewrote the low-level parameterized modules such as transistors and inverters. In addition, he ported and managed the unit and regression tests from SVN to git. Lastly, he improved and implemented multiple dynamically generated memory modules. The goal of OpenRAM is to promote academic research by providing a portable and flexible platform for the generation and verification of memory designs across various technologies, sizes, and components.