UC San Diego

This thesis explores two areas in RF integrated circuits. The first area of work is X-band phased-array design in CMOS technology. A receiver and a transmitter chip is designed, fabricated, measured on-wafer, and then packaged on printed-circuit boards using chip-on-board technique and in QFN modules to verify the reliable operation of silicon chip after packaging. The high-linearity four- element phased-array receiver for 9-10 GHz application is built using 0.13-[mu]m CMOS process with a single-ended design, and it results in a measured gain of 10 dB, an input P1dB 12.5 dBm, and a noise figure of 3.4 dB at 9.5 GHz. An rms gain error of 0.4 dB and phase error of 8° are obtained at 9-10 GHz using an integrated variable gain amplifier and an 11° phase trim bit. The 4-element X-band transmitter chip is also developed in 0.13-[mu]m CMOS technology. The design contains an active 1:4 power divider, active 5-bit phase shifters (lowest bit is used as a trim bit), 4-bit gain control (to reduce the rms gain error), and power amplifiers capable of delivering a PSAT of 13.5 dBm per channel at 8.5-10.5 GHz. The chip can be used in the linear mode for communication systems and in the saturated mode for FMCW radar systems. Packaging based on chip-on-board and QFN modules have been implemented, and both show a very small nearest neighbor coupling of ̃- 30 dB at 8-10 GHz, limited by bond-wire coupling. The second area of work is the switching matrices for high data-rate networking. Two generation of design is implemented and the first-generation is the 0.01-8-GHz 4×4 switch matrix in 0.13-[mu]m CMOS technology. A deep n -well series-shunt-series switch is chosen as the switching core, and the transistor sizes are optimized for low insertion loss and high isolation up to 8 GHz. A full electromagnetic analysis is performed on the switching core to result in a compact design with high isolation. The 4×4 switch matrix shows a measured insertion loss of 2.0-3.3 dB and an isolation of 50-44 dB at 2-8 GHz with near-zero power consumption. The measured input P1dB and IP3 are 8-10 and 26-30 dBm at 0.5-8 GHz. The switching matrix has very low dispersion with 6-ps group-delay variation and can switch a 12.5-Gb/s signal with a bit error rate of <10e-12. The second-generation switching matrix is implemented using IBM 45-nm SOI CMOS process, which offers advanced switch performance. The design is focused on the optical/digital wideband signal networking, and therefore optimization is done to maximize the bandwidth and minimize the added jitter after switching. A cross-point architecture with passive CMOS switch is used to achieve switching with near-zero power consumption. Scalability of all-passive design is maximized by introducing isolation switches placed after every 2×2 switching cells. An inductive-peaking buffers are used on passive-active design in order to further increase the bandwidth of the matrix. The measured 3-dB bandwidth of all-passive and passive-active design are 20-25 GHz and > 26.5 GHz (measurement limit), with very low group delay variation of ±5 and ±2 psec, respectively. The eye- diagram measurement shows that all-passive design can transfer signals up to 30-Gbps and passive-active design can achieve up to 44-Gbps of data-rate. The scalability of passive-active design ensures constant 3-dB bandwidth up to more than 12×12 matrix