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Integrated Tunable Duplexer in CMOS Technology for Multiband Cellular Transceivers


Frequency division duplex (FDD) cellular standards, like WCDMA and LTE, require the simultaneous operation of the transmitter and receiver while sharing the same antenna. A duplexer, currently implemented as two highly selective off-chip SAW filters separates the transmit and receive signals. A high isolation is required to avoid saturating the receiver and keep its noise and linearity requirements feasible. The need for high-Q resonators to implement these filters prohibits duplexer integration in a CMOS process. For each band of a modern multi-band transceiver, an off-chip duplexer is required. With over forty bands currently envisioned for mobile applications, the system cost and complexity rises significantly. Replacing the bank of off-chip duplexers with a single integrated tunable duplexer would enable a fully integrated and reconfigurable multiband transceiver. In this dissertation, the performance of hybrid transformer based integrated duplexer was significantly improved, making it suitable for reliable multiband operation. A hybrid transformer relies on electrical balance rather than frequency selectivity to achieve isolation, making duplexer integration in a CMOS process that lacks high-Q passives possible. Prior demonstrations of integrated hybrid transformer duplexers suffered from high insertion loss, poor common-mode isolation and isolation sensitivity to antenna mismatch. Novel solutions were reached in this research to solve most of these issues. Power recovery by using an RF-DC converter can effectively reduce the loss in the duplexer. A discrete prototype that achieves 60% power recycling efficiency with constant input impedance over wide dynamic range was demonstrated. A differential implementation of the hybrid transformer allows for both high differential and common-mode isolation. Implemented in a 90nm CMOS process, it maintains more than 60 dB of differential to common-mode isolation. And finally, an antenna impedance tracking loop was demonstrated to track any antenna impedance variation and maintain high isolation. Together with a novel high power balance network, that allows high isolation in both the transmit and receive bands, this 65nm CMOS chip achieves an isolation of more than 50 dB in the transmit and receive bands, with an antenna VSWR within 2:1. This work is the first implementation of a CMOS integrated, high-power and antenna mismatch tolerant duplexer

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