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Open Access Publications from the University of California

CMOS RF Power Amplifier Design for Wireless Communications

  • Author(s): FANG, Qiang
  • Advisor(s): Wang, Albert
  • et al.

In recent years, there has been great technology improvement in wireless communication systems. Novel transceiver architectures and circuits have enabled faster data transfer rate over larger area while burning even less power. CMOS technology, by its unique advantages in cost and integration, has enabled an unprecedented level of integration in modern low-cost, small form-factor and low-power wireless devices. The two aspects above put together has made our phones, mp3 players, etc., smarter and smaller, and most importantly, has made our lives more pleasant.

There have been great efforts contributed to integrating the whole transceiver into one single silicon die. However, Radio Frequency (RF) Power Amplifiers (PAs) are still among those few remaining modules that have yet to be successfully integrated. The reduced supply voltage, high on-chip passive loss, and the low breakdown voltage of the thin gate oxide CMOS devices are among the most difficult challenges, which have forced high output power CMOS PAs to operate under large-current and low-impedance levels, where they are vulnerable to parasitic losses. On the other hand, efficiency is a big concern in PA designs. Due to the inevitable power back-off in modern communication systems, it is of great importance to improve the efficiency of a PA when it does not work at its maximum rated power. This work targets two major issues: power combining and average efficiency enhancement. By utilizing on-chip transformer networks and adaptive load techniques, we observe improved efficiency over a wide input range in our proposed PA prototype. And to the author's knowledge, the prototype has the most efficiency recovery points among today's reported fully integrated CMOS PAs.

The proposed PA is designed in a 0.18-um CMOS technology with 1.8-V supply voltage. The obtained linear output power and power gain are 22-dBm and 8.5-dB, respectively, with Power Added Efficiency (PAE) of 12% at 2.4-GHz. The maximum achievable efficiency recovery points during input power back-off are 7. Verification results prove our design methodologies and efficiency enhancement algorisms to be effective. Some relevant research results including Nano-particle Magnetic-cored Inductors (NMIs) and NMI/graphene inductor Voltage Controlled Oscillators (VCOs) are reported at the end of this thesis.

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