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Energy-Efficient VLSI Architectures for Next-Generation Software-Defined and Cognitive Radios

  • Author(s): Yuan, Fang-Li
  • Advisor(s): Markovic, Dejan
  • et al.
Abstract

Dedicated radio hardware is no longer promising as it was in the past. Today, the support of diverse standards dictates more flexible solutions. Software-defined radio (SDR) provides the flexibility by replacing dedicated blocks (i.e. ASICs) with more general processors to adapt to various functions, standards and even allow mutable design changes. However, such replacement generally incurs significant efficiency loss in circuits, hindering its feasibility for energy-constrained devices. The capability of dynamic and blind spectrum analysis, as featured in the cognitive radio (CR) technology, makes chip implementation even more challenging.

This work discusses several design techniques to achieve near-ASIC energy efficiency while providing the flexibility required by software-defined and cognitive radios. The algorithm-architecture co-design is used to determine domain-specific dataflow structures to achieve the right balance between energy efficiency and flexibility. The flexible instruction-set-architecture (ISA), the multi-scale interconnects, and the multicore dynamic scheduling are also proposed to reduce the energy overhead. We demonstrate these concepts on two real-time blind classification chips for CR spectrum analysis, as well as a 16-core processor for baseband SDR signal processing. The blind classifier achieves a 59x lower energy compared to an exhaustive method, while the 16-core SDR processor shows >2.4x higher energy efficiency than state-of-the-art communication processors and closes the gap with functionally-equivalent ASICs to within 2.6x. These techniques not only enable energy-efficient and flexible radio implementation, but can also be applied to other domains of computing.

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