Skip to main content
Open Access Publications from the University of California

Optimizations of manufacturability and manufacturing in nanometer-era VLSI


As optical lithography advances into the 65nm technology node and beyond, minimum feature size outpaces the lithography wavelength. As a result, mask/wafer manufacturing yield improvement and cost reduction have been widely accepted as key factors for aggressive technology scaling. This thesis is concerned with the following four manufacturability/manufacturing problems. Fracturing: Mask manufacturing for the 90nm and 65nm nodes increasingly deploys variable shaped beam mask writing machines. The pervasive use of OPC leads to dramatic increase in the number of thin trapezoids, which significantly decrease the mask manufacturing yield. This thesis suggests an optimal integer linear programming based fracturing approach and a fast heuristics which substantially reduce sliver count in comparison to leading commercial fracturing tools. MPW: Multiple project wafers (MPW) provide an attractive mask manufacturing cost reduction solution for low-volume production designs by sharing the cost of mask tooling among up to tens of designs. This thesis proposes a comprehensive MPW flow aimed at minimizing the manufacturing cost which includes (1) multi-project reticle floorplanning, and (2) wafer shot-map and dicing plan definition. PSM: In the context of wafer manufacturing, Alternating-Aperture Phase Shift Masking (AAPSM) will be used to image critical features on the polysilicon layer at smaller technology nodes. This technology imposes additional constraints on the layouts beyond traditional design rules. Phase conflicts have to be detected and removed to enable the use of AAPSM. This thesis has two key contributions: (1) a new computationally efficient approach to detect a minimal set of phase conflicts, which when corrected will produce a phase-assignable layout; (2) a novel layout modification scheme for correcting these phase conflicts in standard- cell blocks. Redundant Vias: Finally, a large part of wafer manufacturing yield loss is due to via voids, which can be relieved by redundant vias insertion or via doubling. This thesis proposes perfect matching based post -route via doubling which achieves optimum yield improvement. Redundant interconnects or "short loops& quot; are introduced to maximize the number of doubled vias. Experimental results show that near 100% via doubling coverage can be achieved with simultaneously optimal redundant via and short loop insertion in the post -route stage

Main Content
Current View