UCLA

Die-to-wafer (D2W) heterogeneous integration using thermal compression bonding (TCB) faces a serious issues of Cu surface oxidation, and it is uncapable of large-die assembly. Hybrid bonding, on the other hand, is considered as a candidate to replace TCB due to much better resistance to Cu oxidation and its capability for large die integration. Besides this, low temperature hybrid bonding has a great potential to achieve sub-micron pitch assembly because of a room-temperature alignment process. However, the bonding mechanism with real process issues has not yet been fully understood. In this thesis, Finite Element Analysis (FEA) and auxiliary experiments with real process issues have been implemented to explore the mechanism and the window of annealing temperature for the void-free interface. First, silicon dioxide fusion bonding is explored and optimized. A good D2W oxide bonding is achieved with 200 N of shear force (die size is 1.6 mm \times 1.6 mm). The aforementioned real process issues include Cu thickness non-uniformity and real dishing conditions. A Cu thickness variation of 6.6% across the whole wafer after electroplating causes a metal dishing between 4 nm and 16 nm during chemical mechanical planarization (CMP). The critical stress (78.1 MPa) of dielectric material gives the upper boundary of temperature, and the complete contact of metal limits the lower boundary for our FEA models. The window for the annealing temperature is then simulated to be within a range between 295℃ and 302℃. It is the first time that FEA with a non-uniform process input is implemented to generate a process window of D2W hybrid bonding for real world application. This thesis provides in-depth understanding and practical guidance for D2W hybrid bonding.