UC San Diego
10-nm CMOS : a design study on technology requirement with power/performance assessment
- Author(s): Liu, Minjian
- et al.
The scaling of CMOS technology has progressed rapidly for three decades, contributing to the superior performance and dramatically reduced cost per function for modern integrated circuits. As the CMOS dimension, in particular, the channel length approaches the nanometer regime (< 100nm), however, static power dissipation increases precipitously due to increasing leakage currents arising from quantum mechanical tunneling and electron thermal energy. To extend CMOS scaling to 10 nm while still gaining significant performance benefit, alternative device structures or materials are being studied extensively. This work considers the device design and technology requirements of scaling bulk MOSFET to the ultimate limit of 10 nm. For control of short channel effects, the 2-D scale length theory provides a guideline for CMOS device design. A scale length of less than 7 nm is required for 10-nm MOSFET with acceptable short channel effect. High-K dielectric is needed to replace silicon dioxide so that an effective oxide thickness of 0.4 nm can be obtained without inducing detrimental gate tunneling leakage. High body doping level of above 10¹⁹ cm⁻³ is required to control the depletion width to 5 nm. Metal gate would be needed to replace polysilicon gate to avoid poly-depletion effect. Counterdoping in the surface channel layer is necessary in order to lower the threshold voltage to 0.2 - 0.3 V. Also studied in this work are optimum gate-to-source/drain overlap length and the effect of source/drain lateral gradient on circuit performance. An inverse source/drain lateral gradient smaller than 3 nm /decade is needed to avoid excessive source/drain series resistance. Regions where the source/drain doping level drops below 7\times10¹⁹ cm⁻³ should not be left un-gated. In order to manage the increasing active power due to the increasing integration level, the scaling limit of power supply voltage is studied based on noise margin considerations. Mixed-mode simulation of a three-way NAND gate is used to study the minimum noise margin condition with the threshold roll-off taken into account. It is shown that a minimum supply voltage of 0.5 V is required for high performance CMOS circuits