A 2-bit 1Gsps ADC Array with 32:1 Serializer in 45nm CMOS SOI Technology
- Author(s): Tian, Geng
- Advisor(s): Chang, Frank M.C.
- et al.
In this thesis, a SoC (system on chip) solution is proposed for the IF (intermediate frequency) band signal processing and transmission of a radiometer system. This highly integrated and low-power solution is designed for systems where low ADC resolution (< 2-bit) is needed but high-speed data transmission (> 10Gbps) and low-power operation (< 10mW/channel) is strongly desired.
The presented solution includes an array of 2-bit ADCs with duty cycle controlled AGC (automatic gain control) function and a low-power 32:1 serializer. AGC function is included in the front end in order to cope with the wide range of input power (-10dBm ~ -20dBm). The AGC loop is controlled by digitized output duty cycle with an error of 2%. A current steering 5-level tree architecture serializer is designed to achieve a high serializing factor and low-power operation.
The circuit is designed using a 45nm SOI CMOS technology. It is capable of digitizing the IF signals using a power of 5.4mW/channel and transmitting the signals at 32Gbps. The serializer has an output reflection (S22) of less than -10dB from DC to 32GHz with 400mV differential output swing. The serializer consumes less than 50mW of power (3.2mW/channel), and the AGC loop consumes 2.2mW/channel.