UC San Diego

The performance of phase-locked loops (PLLs) is critical to advancing the data rates in wired and wireless communication systems. Most PLLs incorporate either analog filters and voltage-controlled oscillators (VCOs) or digital filters and digitally-controlled oscillators (DCOs). The former are called analog PLLs and the latter are called digital PLLs. To date, analog PLLs have the best phase error performance, but digital PLLs occupy smaller active area, lend themselves better to digital calibration and signal processing techniques, and are more compatible with highly-scaled CMOS integrated circuit (IC) technology. Thus, improving the performance of digital PLLs has been the subject of intensive research for many years.The first chapter of this dissertation presents an incremental frequency control (IFC) scheme for DCOs comprised of an arbitrarily large bank of unit-weighted frequency control elements (FCEs). The scheme requires only a pair of differential 1-bit control signals, is inherently monotonic, and avoids transient frequency glitches. Measurement results are presented to demonstrate the functionality of the proposed frequency control scheme and its negligible impact on a PLL’s locking time and phase noise. The second chapter of this dissertation presents a reference frequency-doubling (RFD) technique that is immune to crystal oscillator duty-cycle error and is not subject to the speed-accuracy trade-off associated with conventional duty-cycle error calibration techniques. The technique is presented and analyzed in the context of a delta-sigma frequency-to-digital converter (ΔΣ-FDC) based PLL. Analysis and behavioral simulations with nonideal circuit parameters show a 10× improvement in the worst-case convergence time compared to prior art. The third chapter of this dissertation describes a parasitic-capacitance-induced nonlinearity mechanism in charge pumps (CPs) used in fractional-N PLLs, along with a scheme to mitigate it. Presented in the context of a 10 GHz ΔΣ-FDC based PLL, behavioral simulations with nonideal circuit parameters show that the proposed technique reduces the PLL’s fractional spurs’ level by more than 10 dB, achieving a worst-case in-band spur level below −54 dBc and an integrated RMS jitter below 80 fs. The fourth chapter of this dissertation presents a system architecture review, along with behavioral simulation results, for a 9–11 GHz ΔΣ-FDC PLL IC, targeting 75 fsrms jitter.