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Efficient cache-coherent migration for heterogeneous coprocessors in dark silicon limited technology
Abstract
Current trends in processor manufacturing indicate that in order to meet power budgets, chips will have to power-gate an increasing fraction of transistors. This so called dark silicon will play an important role in motivating future architectures. Recent research proposes to allocate these large dark regions to power-efficient specialized coprocessors. GreenDroid is a tiled architecture where each tile includes a set of coprocessors, generated at design time, that target the anticipated workload. A central challenge to retaining the efficiency of this system is providing low overhead migration mechanisms so that tasks can move around the chip to exploit different coprocessors. This thesis presents a prototype migration system for GreenDroid and other tiled coprocessor-based architectures. The results show that for single-threaded irregular workloads, migration between c-cores spread across a four-tile configuration can provide power savings from 4.8x to 6.2x compared to an all software approach on a single tile. When compared against an ideal case where all c-cores fit on a single tile, the energy overhead of migrating amongst tiles ranges from 2.6% to 24.1%
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