UC Berkeley

Electronic monitoring utilizing process-specific Ring Oscillators (RO) is explored as a means of identifying, quantifying, and modeling sources of variation in circuit performance due to manufacturing and layout design parameters. This dissertation contains the first measured silicon results for the utilization of parameter-specific modification of ring oscillator layouts to electronically monitor particular process variation. Design and testing for this work were made possible through the Berkeley Wireless Research Center. The working circuits were fabricated by ST Micro in a 45 nm fabrication process that was under development.

The design was based on a process design kit provided by ST Micro. The lithography simulation was carried out using generic models in Mentor Graphics Calibre. Five systematic process effects were considered: etch, focus, misalignment, and capping layer and Shallow Trench Isolation (STI) stress. In all cases, inverter layouts were modified in order to increase sensitivity to a particular parameter within design rule constraints. For monitoring etch, the presence or absence of adjacent dummy gates and pre-correction for residual lithographic effects were used. For monitoring gate focus, spillover functions and Pattern Matching were used as an initial guide to place added surroundings to the gate; this was followed by systematic optimization via Mentor Graphics Calibre simulations. A focus sensitivity of 1.5 times that of a dense gate was achieved. For monitoring gate-to-active misalignment, a set of 5 pre-programmed offsets on an `H-shaped diffusion' was designed. The RO frequency versus offset relationship in design showed a parabolic shape with a speed up of 3.2% for 15nm misalignment. The capping layer and lateral STI stress monitors were designed based on changes in the lateral size of the source and drain, including those of asymmetrical source/drain areas.

Seventeen chips were received, packaged, and automatically tested. The measured range of the across-wafer variation was 11.1% for control-case RO with minimum sized gate area. For a given monitor on a typical chip, the variation among the 36 RO instantiations normalized to its mean is 0.2-0.3 %, with the larger value occurring for the smaller gate areas. When these values were multiplied by the square root of the product of 36 instances time 26 transistors per RO, the average threshold slope (AVT) of 2.3mV/um was obtained in an equivalent Pelgrom model.

The measured RO frequency sensitivity to gate focus monitors shows that they are about 4% slower than the control ROs. This decrease is attributed to parasitic effects as well as the non-uniform `hour-glass' shape produced at the top and bottom of the gate from the horizontal extensions used to increase focus sensitivity. The pre-programmed gate-to-active misalignment monitors show a 2-4 nm overlay error for 17 chips. The fact that the experimental measurements are less sensitive than predicted during the design stage is in part attributed to the fact that the wafer was run under unusually good control without any programmed treatments such as defocus. This observation is supported by the fact that the measured range of RO frequency was typically centered and 1/6-1/4th of the SS-FF guard band. The unanticipated requirement to apply strong OPC techniques with scatter-bars to the monitor designs in order to guarantee that they would not impact product yield also resulted in considerable sensitivity loss.

The Nitride Contact Etch Stop Liner (CESL) strain-induced monitors show a ring oscillator frequency increase of 5.3% and 13.9% for 1.8X and long length source/drain diffusion (LOD) respectively as compared to minimum LOD, after the normalization of raw data to simulation data so as to correct for parasitic effects. This increase is due to increased CESL-induced strain for large LOD. For the same LOD, asymmetrical designs show a 3% ring oscillator frequency increase for larger source LOD than that of larger drain LOD, indicating transistor injection velocity as well as mobility is important.

The random variation of RO circuit performance for a given layout monitor within a chip is examined for 3 sources of variations: changes in gate length (L), gate oxide thickness (Tox), and channel doping (Nch). The strategy here is to make a linear approximation of the measured RO frequency sensitivity to these 3 parameters under 5 distinct combinations of operating voltages and temperatures using the 45nm PDK BSIM4/PSP models. The strategy is implemented using least mean square (LMS) analysis. For all of the blocks, the LMS results indicate that the source of random within-chip variation is dominated by random dopant fluctuations in comparison with changes in L and Tox.