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Low-Power Wireline Transmitter Design


With the recent surge in the demand for high data rates, communication over copper media faces new challenges. First, the limited bandwidth removes so much of the signal's high-frequency energy that equalization and detection become very difficult. Second, the greater data rates in serial links inevitably translate to high power consumption. State-of-the-art transmitters operating in the range of tens of gigabits per second draw hundreds of milliwatts, underscoring the need for new circuit and architecture techniques that can ease the trade-off with speed.

The first part of this research introduces a 40-Gb/s non-return-to-zero transmitter that improves the power efficiency by a factor of 2.28. This is accomplished through removing power-hungry retimers in transmitter front end, merging the output driver and the final multiplexer stage, proposing a current-integrating multiplexer and "latchless" feedforward equalization path. Implemented in 45-nm CMOS technology, the transmitter provides 7.4-dB boosting and draws 32 mW at 40 Gb/s.

The second part of this research studies the design of an 80-Gb/s PAM4 transmitter that achieves nearly six-fold improvement in power efficiency with respect to state of the art. With a two-fold reduction in bandwidth occupancy compared to non-return-to-zero data, the PAM4 format allows significant speed improvement but also introduces other issues such as skew and linearity. The design introduces a number of novel ideas so as to achieve both a very high data rate and much lower power consumption compared to state of the art. In particular, the design proposes a "latchless" serializer architecture, a charge-steering multiplexer, and a high-speed divide-by-two circuit that directly generates outputs with a 25% duty cycle. These techniques culminate in the 80-Gb/s PAM4 transmitter, including an on-chip phase-locked loop, that draws only 44 mW in 45-nm CMOS technology.

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