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Benchmarks for the 1992 high level synthesis workshop

  • Author(s): Dutt, Nikil
  • Ramachandran, Champaka
  • et al.
Abstract

This report describes the current status of benchmarks for the 1992 High-Level Synthesis Workshop and suggests guidelines for benchmark submission. The benchmark set currently has 9 designs, where each benchmark includes a VHDL description of the design, documentation of the design's functionality, as well as a set of test vectors and expected outputs for simulation. Documentation of the testing strategy the test vectors are also provided with each benchmark. Although the benchmarks are currently written in VHDL, we have attempetd to organize the benchmarks in a language-independent format so that users can easily translate the benchmarks into their favorite HDL; the representative set of test vectors and expected outputs allow a user to ensure, with some level of confidence, that their HDL descriptions preserve the original behavior of the benchmarks. The current benchmark set contains designs that exercise different types of functionality (e.g., DSP, FSM-based, arithmetic, etc.), as well as different types of HDL behavioral constructs (e.g., nested loops and nested conditionals). We conclude with a suggested set of guidelines for benchmark submission.

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