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High-Voltage Generation and Drive in Low-Voltage CMOS Technology

  • Author(s): Ismail, Yousr
  • Advisor(s): Yang, Chih-Kong Ken
  • et al.
Abstract

High-voltage dc and switching waveforms are needed in many of today’s electronic systems. Various MEMS applications require output voltage signals that are several 10's of volts. Advanced CMOS technology nodes allow for smaller, lower-cost electronics, but are not engineered to handle such high voltages directly. High-voltage systems are often implemented in older, voltage-tolerant technology nodes or other specialized processes; driving the overall system size and cost up.

This dissertation introduces technology and circuit methods that extend the voltage range of a standard, fine-linewidth CMOS process beyond its conventional breakdown limit. Examples of high-voltage generation and drive circuits introduced in this dissertation include: 1) voltage charge pumps and 2) output voltage drivers. The introduced circuits are fully compatible with standard low-voltage CMOS process and maintain long-term device reliability.

For high-voltage generation, we introduce a new Hybrid Charge Pump architecture. The hybrid architecture extends the voltage tolerance of a nanometer scale CMOS substrate by ~8x while enabling improved power efficiency. We provide an analytical power model for the Hybrid Charge Pump, and outline a systematic method to optimize its power efficiency. For high-voltage drive, we introduce a Charge Pump-Based output stage suitable for driving high-impedance loads. The output driver enables seamless stacking of 10's of devices with little power and area overhead, enabling output waveforms with extended voltage ranges in a low-voltage CMOS process.

Practical results presented in the dissertation include the measurement results of a 36V 49% efficiency Hybrid Charge Pump in 65nm bulk CMOS technology, and a bipolar 44V Charge Pump-Based driver with a 21KΩ output resistance in 45nm SOI CMOS technology.

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