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2D-Material-Channel Field-Eect Transistor for VLSI

  • Author(s): Zhang, Ming
  • Advisor(s): Woo, Jason C.S.
  • et al.
Abstract

2D materials have attracted tremendous attention for a variety of properties such as ultra-low body thickness, ultra-high mobility, tunable bandgap, etc. These unique merits of the 2D materials bring in the significant improvements and new perspectives in the digital CMOS scaling, analog performance, as well as the 3D integration of the wafer stacking. In this dissertation, two kinds of 2D materials, namely the graphene and molybdenum disulfide(MoS2), have been closely examined through material synthesis, device simulation and performance optimization.

Among these 2D materials, graphene is well known for its high mobility and high saturation velocity, which makes it a promising candidate in the analog device, where high transconductance and cut-off frequency is mostly appreciated. To integrate of such device into the traditional Complementary-Metal-Oxide-Semiconductor(CMOS) technology, the chemical vapor deposition of graphene sheet is reviewed and studied as a viable synthesis method. The growth of graphene using copper as catalyst has been carried out using a resistive-heating tube furnace. The Raman spectra of the thin film synthesized on the copper foil, blanket copper film and patterned copper dots are demonstrated and analyzed. It is found that the concentration of copper vapor plays a critical role in the quality of deposited graphene film. In addition, the copper-vapor-catalyzed growth directly on the insulating film has been reported and fabricated into device.

Simulation on the field effect transistor(FET) using graphene as channel is carried out based on the drift-diffusion model. Simulated characteristics are compared with the experimental results based on the extracted value. By using the contact resistance model, it is found that the source/drain resistance shows substantial impact on the on-state current of the transistor. This is because the voltage drop on the resistance dominates the carrier concentration in the pinch-off region, which limits the on-current.

In order to improve the contact resistance, three different metal contacts have been adopted for graphene transistor, from which, the contact resistivity is extracted with its transfer characteristic. Among Ti, Ni and Pd, palladium shows the lowest contact resistivity to graphene around 5e-6 Ohm cm^2. Meanwhile, the carbon layer directly deposited on SiO2 substrate is examined by its transfer characteristic. The similar transconductance but different level of the drain current, shows that longer deposition time only increases the thickness of the carbon layer rather than the mobility.

Unlike graphene, MoS2 with reasonable band gap and the ultra-thin body exhibits its potential in improving the short-channel effect, and in return, increasing the on-current. Nevertheless, the simulation on the MoS2 transistor under drift-diffusion model shows otherwise down to the physical channel length of 10nm. Though MoS2transistor improves the short-channel behavior, such as Drain-Induced-Barrier-Lowering (DIBL) and Subthreshold Swing (SS), the on-current of the MoS2 transistor shows no increase in comparison with strained Silicon-On-Insulator (sSOI) device and FinFET structure during the brutal-force scale-down of gate length.

However, MoS2 can still be a promising candidate to thin film transistor and an option in the 3D integration for integrated circuits. The synthesis of MoS2 is achieved through the sulfidation of pre-deposited MoO3 film on the insulating substrate. A post-sulfidation process is adopted to improve the quality of 2D material, which is closely related to the duration (shown by the sheet resistance in transmission line structure).

The effect of rapid thermal annealing(RTA) on metal to MoS2 contact is demonstrated by the I-V curve of the transmission line structure before and after RTA process. The improved linearity shows the elimination of the gap between the metal and semiconductor. Meanwhile, different metals have been deposited as the source/drain and the contact resistances are extracted, where Ti/Au shows better overall resistance. The non-linearity between the resistance and channel length is explained and fitted by the transmission line structure on low-doped SOI (silicon on insulator). The performance of MoS2 FET has been demonstrated using Ti/Au contact.

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