UCLA

At the UCLA Center for Heterogeneous Integration and Performance Scaling (CHIPS), we are focused on advancing wafer-scale systems with fine-pitch, scalable interconnections to meet the growing demands of artificial intelligence (AI) and high-performance computing (HPC). One of the main challenges in our Silicon Interconnect Fabric (Si-IF) wafer-scale system is the integration of capacitors to ensure efficient power delivery and maintain signal integrity. While traditional printed circuit boards (PCBs) easily achieve desired capacitance with discrete components, integrating capacitors into the Si-IF presents significant challenges in both structure design and fabrication processes. This thesis explores the design, development, and integration of Metal-Insulator-Metal (MIM) capacitors into the Si-IF platform. The work begins by selecting appropriate dielectric and electrode materials for the capacitors, considering their electrical performance and compatibility with the Si-IF process. A comprehensive process flow is developed, from initial structure design to fabrication, with a focus on optimizing the capacitor structure to improve process feasibility. The results demonstrate that the proposed MIM capacitor structure can be successfully integrated into the Si-IF platform. Electrical characterization of the test structures further validates the performance and effectiveness of the design. This research provides a viable path for incorporating capacitors into wafer-scale Si-IF systems, offering a solution to the power and performance challenges faced by AI and HPC applications.