UC San Diego

Increasing variability in today's manufacturing processes causes parametric yield loss that increases manufacturing cost. In spite of the tremendous effort and enhancement from both manufacturing and design sides, problematic systematic variations still remain uncompensated. In addition, while new manufacturing techniques have been adopted to reduce variability by improving pattern fidelity in the subwavelength lithography regime, new techniques continually introduce new sources of variabilities. To mitigate any remaining or emerging variabilities, accurate modeling and assessment of the variabilities through detailed analyses of underlying physical mechanisms is essential. Appropriate optimizations in both design and manufacturing must be developed, based on comprehensive understanding of the benefits and costs of such new measures. This thesis first quantifies impact of guardband reduction on design outcomes, and resulting yield and cost, to objectively evaluate the true benefits of various guardband reduction techniques. Cost-effective guardband reduction techniques are then presented for both design and manufacturing. The proposed measures span multiple stages of design, manufacturing and implementation : (1) from basic circuit elements such as device, interconnect, logic gates and memory bitcells, to high-level design implementation phases such as logic synthesis, placement and routing, and (2) from mask generation and lithography, to post-silicon variation measurement. The innovative techniques proposed in this thesis can be grouped into three main thrusts : (1) variability modeling and mapping, (2) variation assessment, and (3) variability mitigation. In the variability modeling and mapping thrust, this thesis reviews various variation modeling techniques and proposes a novel variation mapping framework (based on compressed sensing theory) that reconstructs the details of multiple, simultaneously occurring systematic variation maps from measurements of a small number of naturally occurring timing paths within the design. In the variability assessment thrust, this thesis proposes techniques to quantify variability in advanced lithography techniques, such as double patterning lithography and interference- assisted lithography, and provides useful observations for designers and manufacturers to tradeoff quality of results versus design and manufacturing cost. In the variability mitigation thrust, this thesis presents three distinct approaches to explicitly mitigate variations and enable principled tradeoffs between design cost and yield. First, design-aware manufacturing process optimization provides optimal mask strategies considering parametric and defect yields, and optimal exposure dose maps considering design timing and leakage power. Second, manufacturing-aware design optimizations include a cell swapping-based placement optimization, timing yield-aware detailed placement optimization to mitigate impact of bimodal CD distribution in double patterning lithography, and development of a new 1-D regular pitch SRAM bitcell for interference-assisted lithography. Finally, design- manufacturing co-optimization includes a first-ever elucidation of the tradeoff between electrical performance and manufacturing cost for modern transistor fabrication