UC Berkeley

Scaling transistors is good for speed but scaling interconnect degrades it due to resistances and parasitic capacitances. Scaling of supply voltage VDD has significantly slowed down since the 130 nm node. As a result, integrated circuit (IC) power consumption has been on the rapid rise. Crosstalk noise problem has been also increased as scaling. Reducing capacitance is an excellent solution for these problems; the circuit delay, power consumption, and crosstalk noise. The future transistor and interconnect with lower capacitance should be considered to overcome these problems. An air-gap structure can be attractive solution for both transistor and interconnect. Novel air-gap structures are proposed in this research. In the transistors, the conventional spacer structure is replaced with air-gap spacer structure. This new structure leads for the fringing capacitance to be decreased much. Therefore, the speed and power consumption can be improved. This structure can be compatible with both the conventional gate-first and gate-last process. Other designs involve use of self-aligned contact or linear contact processes to achieve a much more effect. The low-k spacer transistor which is included this air-gap spacer transistor degrades the current performance. Thus, the air-gap spacer technology is very helpful to the high performance devices but it is not much helpful to the low stand-by power devices. The corner spacer transistor with high-k inner spacer and low-k outer spacer is proposed to overcome the degradation of current performance. The high-k material can improve the current performance and the low-k material can improve the capacitance. In the interconnects, the proposed novel air-gap interconnects are compatible with both the subtractive etch interconnect and dual damascene interconnect. These air-gap structures can improve not only the effective dielectric constant but also crosstalk noise problem.