Multi-Port Automation for SRAM Compiler Design
Memory compilers are useful in computer system design as they automate layout, netlists, and characterization of a memory. This thesis presents a multi-ported SRAM scheme for the open-source SRAM compiler OpenRAM. This multi-ported SRAM design has access ports configurable to read and write, write-only, or read-only and supports any number of ports in any combination. I designed layout automation for an array of these bit cells in a generic 45nm process and fabricable 180nm SCMOS. I designed netlist automation for the entire memory system for any combination of ports. A functional test I've designed automates SPICE simulations on the top level netlist to verify any port configuration.