UC Santa Cruz

The study on verification trends in the semiconductor industry shows that the design complexity is increasing, fewer companies achieve first silicon success, companies hire more verification engineers, and 53% of the whole hardware-design-cycle is spent on design verification. The cost of a re-spin is high, and more than 40% of the cases that contribute to it are post-fabrication functional bug exposures. The study also shows that 65% of verification engineers' time is spent on debugging, test creation, and simulation.

In this dissertation, I discuss tools and methods that improve the effectiveness and productivity of microprocessor verification. In particular, first, I discuss Dromajo, the state-of-the-art processor verification framework for RISC-V cores. Dromajo is an RV64GC emulator that was explicitly designed for co-simulation purposes. It can boot Linux, handle external stimuli, such as interrupts and debug requests on the fly, and can be integrated into existing testbench infrastructure with minimal effort.

Second, I address a significant limitation of co-simulation as a technique. Previously, it had been impossible to co-simulate multi-core processor configurations. In this dissertation, I talk about Marionette Models, a methodology that, for the first time ever, enabled the co-simulation of microprocessor designs in multi-core settings.

Finally, I discuss Logic Fuzzer (LF), a novel tool that expands the verification space exploration without the creation of additional verification tests. The LF randomizes the states or control signals of the design-under-test at the places that do not affect functionality. It brings the processor execution outside its normal flow to increase the number of microarchitectural states exercised by the tests.