UCLA

Domain-specific accelerators deliver orders-of-magnitude gains in performance and energy efficiency, but each remains a bespoke, multi-year hardware and software effort, confining custom acceleration to a few organizations and stable domains. This dissertation shows that complete programmable accelerator systems — computational fabrics, memory systems, on-chip networks, and their compilers — can instead be produced by automated, evidence-driven, full-stack design space exploration.Four systems form a connected lineage, each widening the automatically explored scope. DSAGEN synthesizes single programmable spatial accelerator cores: hardware is a mutable graph of decoupled-spatial primitives, compiled by modular transformations that adapt to the graph’s features, and explored with a schedule-repairing spatial scheduler; its compiler reaches 89% of manually tuned performance across five reproduced spatial architectures, and its explorer’s designs average a 1.3× performance2/mm2 advantage over prior programmable accelerators. OverGen scales the explored object to a complete multi-core system-on-chip deployed as a runtime-programmable FPGA overlay, co-exploring tile fabrics with shared cache, network, and data-reuse provisioning; validated on FPGA hardware, it outperforms an untuned state-of-the-art high-level-synthesis design-space explorer by 1.2× geomean while compiling four orders of magnitude faster and reconfiguring in microseconds. OverNoC characterizes the hardened networks-on-chip of multi-chiplet FPGAs and composes hierarchical hybrid network overlays that support implemented networks up to 1.7× larger than the flat hard NoC and, with gains unlocked by near-data placement, deliver 2.5–3.3× speedups on three of four applications; scratchpad-limited matrix multiplication gains only 1.7× and slightly regresses against an equally optimized flat network. Loom consolidates the lineage into a full-stack compiler and exploration framework for heterogeneous multi-core spatial accelerator systems, built on a single semantic source of truth for hardware, immutable content-addressed artifacts, and a central evaluation substrate tying every layer into one reproducible feedback loop; validation spans drop-in compilation of an 892-operator-execution corpus dominated by unmodified vendor libraries and gem5-backed full-system execution of real applications, with the equal-area heterogeneous-versus-homogeneous comparison identified as the open frontier.Together, these systems demonstrate that the unit of automated design can grow from a datapath to a heterogeneous system without design effort growing with it: when design becomes compilation, iteration becomes cheap, and the evidence — not the designer’s habit — chooses the architecture.