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Compact modeling of quantum effects in double gate MOSFETs

Abstract

As CMOS scales down to the limits imposed by oxide tunneling and voltage non-scaling, double-gate (DG) MOSFET has become a subject of intense VLSI research. In this dissertation, quantum effects were investigated in both long channel and short channel Double-Gate MOSFETs. A 1-D numerical Poisson-Schrodinger solver was developed for the quantum solutions in DG MOS structure. The solver can be expanded for the current characteristics of DG MOSFETs because of equivalent influence of the quasi-Fermi potential and the gate voltage on the inversion charge density. Through extension solutions in symmetric DG MOSFETs, quantum effects induced threshold voltage shift was expressed as a close form function of the silicon thickness based on a physical approximation. The gate capacitance degradation due to quantum effects was modeled by the inversion layer thickness change, which can be extracted from the inversion charge density. Quantum I - V and C - V characteristics were generated by the analytical classical potential model with the threshold voltage and gate capacitance degradation implemented as quantum corrections. Complicated quantum mechanical behavior of electrons in asymmetric DG MOSFETs was investigated. The threshold voltage shift can be calculated with the electron ground state energy calculated through different methods. An equivalent small-signal capacitance circuit was developed to model the charge coupling between the two gates and inversion channels. The capacitance model was valid for different types of DG MOSFETs and different operation region. A 2-D analytical potential solution to the Poisson's equation was incorporated into the Schrodinger equation for the quantum solutions in short channel DG MOSFETs. With the eigen energies calculated through the perturbation method, quantum subthreshold current was calculated. The results agreed well with the simulated data by an iteration procedure. The quantum threshold voltage shift and sunthreshold slope in short channel DG MOSFETs were expressed as close functions of device parameters and bias, which can easily be implemented into the classical model

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