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A 56-Gb/s 8-mW PAM4 CDR with High Jitter Tolerance

  • Author(s): Hou, Guanrong
  • Advisor(s): Razavi, Behzad
  • et al.
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Advancement in smart devices, development in cloud computing, and surge in Internet usage means an ever fast increase in demand for wireline communications, which include very-short-range chip-to-chip communications, data center interconnections, cross data center interconnections, and metro and long-haul communications. Four-level pulse-amplitude-modulation (PAM4) is proven to be the latest trend and replacement for traditional non-return-to-zero (NRZ) standards. Of current PAM4 standards, 56-Gb/s is one of the popular data rates to realize wireline data communication.

In PAM4 wireline communications, clock and data recovery (CDR) circuit is one of the most important building blocks, without which it is impossible to receive the correct input data and realize wireline data communication. In most applications, a typical CDR decides recovered clock jitter, loop bandwidth, and jitter tolerance. Regarding power consumption, for line-side applications, a CDR takes a significant amount of power (20% in some cases); while for host-side applications, a CDR uses most of the power. Therefore, we would like a CDR that has low recovered clock jitter, high jitter tolerance, low power consumption, and a proper loop bandwidth depending on specific standards.

A review of current works shows that, most recent PAM4 CDRs are still slicer based or ADC/DSP (Analog-to-Digital-Converter/Digital-Signal-Processing) based, which means an incoming PAM4 signal is transformed into NRZ signals first, and then they are processed with traditional NRZ approaches. Slicers or ADC/DSP usually lead to high power consumption, and/or heavy calibration.

This work proposes a new 56-Gb/s PAM4 CDR architecture. It uses a proposed phase detector (PD) design that processes PAM4 signal in analog domain by generating Euclidean distances among the samples. This work also proposes an analog background offset-cancellation scheme that makes the PD robust.

Realized in 28 nm CMOS technology, the CDR prototype consumes a total power of 8 mW. It has a 547-fs recovered root mean square clock jitter for a 160-MHz loop bandwidth and at least 1 unit interval (UI) jitter tolerance (BER < 10^-12) at 10MHz.

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This item is under embargo until May 13, 2023.