III-V Multigate Non-Planar Channel Transistor Simulations and Technologies
- Author(s): Shih, Kun-Huan
- Advisor(s): Chui, Chi On
- et al.
As the relentless scaling of conventional Si CMOS transistors continues, it becomes more and more challenging to further increase device drive current and reduce leakage current and power consumption. III-V multigate non-planar channel transistors have emerged as a promising contender in the post-Si era due to its high carrier mobility and superior electrostatic control of the non-planar structure. For device design, current Technology Computer Aided Design (TCAD) modeling, however, fails to accurately predict device behaviors in decananometer dimensions. Further, for the analog/RF applications, parasitics engineering plays a determining role in an ultrathin body structure but the conventional symmetric source (S) / drain (D) architecture restricts design and optimization versatility. Moreover, for III-V transistors fabrication, the device-level co-integration capability is crucial but still not mature in current technology.
In this work, a systematic methodology is developed to calibrate TCAD hydrodynamic model against Monte Carlo (MC) simulation in the quasi-ballistic regime. Good fits of both IDS-VGS and IDS-VDS curves have been demonstrated at various device dimensions. This methodology facilitates an accurate and time-efficient device simulation. Secondly, we explore a GaAs accumulation mode vertical transistor for asymmetric S/D design and optimization. Separate control of S/D spacer thickness and underlap length can be implemented and their individual impact on analog performance is discussed. Device design guidelines for different analog/RF metrics improvement are presented. Thirdly, we develop a VLSI-compatible top down process with co-integration capability in III-V multigate non-planar channel transistor fabrication. Nanowires are patterned by photolithography and etching of a source substrate and transferred to another receiving substrate by transfer stamping. A VLSI cleanroom tool is used in the transfer process to accurately position nanowires. This technique yields large arrays of aligned GaAs nanowires, and facilitates device-level co-integration of III-V multigate non-planar channel transistors on the same substrate with close proximity and overlay accuracy.