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Baseband and LO Techniques with Integrated CMOS for Wideband Millimeter-Wave Sensing

  • Author(s): Zhang, Yan
  • Advisor(s): Chang, Mau-Chung Frank;
  • Madni, Asad M
  • et al.

Millimeter-wave circuits and systems are fundamental building blocks in scientific instruments for space and Earth exploration. One important class of such instruments is radio frequency (RF) spectroscopy with frontends operating at sub-millimeter wavelengths. Modern missions prefer cheaper, smaller, and more efficient components for multi-pixel and multi-sensor integration. This dissertation exams building blocks of RF spectroscopy and presents efficient baseband and LO designs in integrated CMOS technology for instrument minimization.

This work started with the development of three generations of RF spectrometer SoCs, where CMOS devices takes the more traditional role in baseband processing. Emphasis is given to the design, optimization, and implementation of high-speed and high-channel-count real-input FFT cores with specialized pre- and post-processing requirements. Optimization techniques at the algorithmic (zero-padded complex FFT), architectural (parallel-pipeline partition and extended Radix-2K factorization), and algebraic (linear approximation, constant multiplier, and tapered bit depth) levels allows the designs to fit in compact floorplans with limited routing resources at up to 12GHz equivalent speed. The FFT cores are among the largest and the most efficient designs for high-speed applications whereas the SoCs represents the first dedicated spectroscopic processors with the highest level of integration.

The second part of this dissertation, breaking away from convention, explores the use of CMOS digital inverter rings for ultra-wide millimeter-wave frequency synthesis as a compact and scalable alternative to high-order LC networks. Based on ring oscillator scaling properties and the optimal conditions for superharmonic injection locking, a new methodology is proposed to co-design robust multi-ratio VCO-ILFD pairs. Put in a cascaded PLL, the fabricated prototype covers 23-39GHz with phase noises below -96dBc/Hz at 1MHz offset. Further improvement can be easily achieved with better device and passive modeling. Additional reconfigurable frequency multiplier is also proposed to take advantage of the quadrature output for tri-band (28/39/60-GHz) LO generation.

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