UC Santa Cruz

Reduced form-factor in portable electronics has made energy-efficiency the primary target. Subthreshold operation is a low-power technique delivering significant energy efficiency. However, circuits in subthreshold are very sensitive to process variation. Utilizing subthreshold operation and leveraging energy efficiency necessitates compensation techniques to mitigate process variation.

The specific contributions of this thesis are: design and implementation of a subthreshold FPGA chip using body bias as a compensation mechanism against threshold voltage variation. Analysis of performance and energy of a subthreshold FPGA using a high-level characterization framework. Using this framework, the minimum energy point of the subthreshold FPGA was found to be in deep subthreshold, and a performance window of 30x with a 2x energy range was identified. A design methodology to mitigate threshold voltage variation by delivering optimized and adaptive body bias in circuits with standard cells. Using two algorithms, this methodology produces standby energy savings of up to 21.06% on average and active energy savings of up to 18.84% on average.