High-Bandwidth Memory Optimization and Hierarchical Partitioning of Reconfigurable Neuromorphic Systems
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High-Bandwidth Memory Optimization and Hierarchical Partitioning of Reconfigurable Neuromorphic Systems


Neuromorphic computing aims to emulate the highly adaptive and efficient processing of the biological brain in silicon. Field-Programmable Gate Arrays offer a way to create general-purpose reconfigurable neuromorphic systems that when coupled with High-Bandwidth Memory are able to offer massive parallelism and throughput. Using these advances, we aim to build a general-purpose neuromorphic computing platform be broadly available to the general research community. This real-time system is reconfigurable, operates in real-time, and implements highly flexible neural dynamics with up to 160 million neurons and 40 Billion synapses. The first part of the thesis discusses the overall system algorithm and investigates the organization of creating an interface between a potential user and the entire reconfigurable platform. We discuss the creation of an intermediate representation for our reconfigurable system. We show the algorithms used in order to map from an intermediate representation of the network into either the High-Bandwith Memory or the python simulator. Finally, we discuss optimization algorithms that can be used to improve both memory savings and execution speed on the network. The second part of the thesis focuses on an efficient and scalable method for large-scale network partitioning on this neuromorphic system across different layers of hierarchy. The partitioning method results in a balanced assignment of neurons to each core in the network while providing flexibility to any input network structure. We demonstrate results on various input networks and compare different system router configurations in order to show the improved performance of the partitioning algorithm.

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